1. Field of the Invention
The present invention relates to a linear feedback shift register and, more specifically, to a linear feedback shift register useful for a design for testability of an LSI (large scale integrated circuit), a VLSI (very large scale integrated circuit), and a ULSI (ultra large scale integrated circuit), in particular for a built-in self test of these circuits.
2. Description of the Related Art
In accordance with great progress in semiconductor technology, a VLSI chip which is larger, more complicated, with higher performance than an LSI chip, has appeared, and a ULSI chip will make its appearance in the near future. The problem of how these chips are to be tested has become very serious. A conventional LSI chip is generally tested by an LSI tester using its function only for a normal operation. The VLSI and ULSI chips need a great number of test vectors and, accordingly, the efficiency of an LSI tester required to test these chips becomes higher and higher. Since, further, an objective judgement of to what degree the chips are tested by the test vector has to be made separately, a CPU cost is greatly increased.
As is evident from the above, it is actually almost impossible to completely test the VLSI and ULSI chips by the conventional method. To solve the above problem, a design for testability capable of perfectly testing a chip at low cost by incorporating a test circuit in advance into the chip, has lately attracted attention and become popular.
In a built-in self test (referred to as BIST hereinafter) which is one type of the designs for testability, an LSI chip to be tested as a device under test (referred to as DUT hereinafter) incorporates a test data generation circuit and a test result generation circuit to start the test in response to an externally supplied signal and, after the test, output a pass/fail result signal or a test result data. This test hardly requires an LSI tester and is considerably effective in reduction in test cost. Moreover, the chip can be tested under the same condition as in the case of the actual use thereof, as can be the chip incorporated into a system. In view of these advantages, the BIST is expected that it will be remarkably important to the VLSI and ULSI chips.
The most basic technique of the BIST described above is signature analysis using a linear feedback shift register (hereinafter referred to as LFSR).
First the LFSR will be described.
The LFSR (n bit width) can be used as both a test data generation circuit and a test result generation circuit. The LFSR (n=8) serving as the test data generation circuit is, as shown in FIG. 1, a simple register circuit including serial-connected n D-type flip-flops (referred to as F/F hereinafter) and a feedback circuit for generating an exclusive-OR (referred to as XOR hereinafter) signal of outputs Q of predetermined F/F and supplying it to an input terminal D of the first one of the serial-connected F/F.
The initial value other than all-0 is set to the F/F to operate the LFSR (whose initializing circuit is omitted in the figure). 2.sup.n -1 of random data (pseudorandom numbers), which are the maximum numbers obtained from the LFSR, are repeatedly output in predetermined order. The random data can be sequentially taken out by using any one of outputs Out.sub.i (i=0, 1, . . . , 7) of the F/F, or they can be taken out in parallel by using all these outputs.
The latter technique using all the outputs of the F/F is generally-used in and important to the recent VLSI and ULSI of multi-bits for processing data.
The signature analysis is a technique of using the LFSR as a test result generation circuit and, in this case, the LFSR comprises an LFSR for inputting the outputs of the DUT in serial and an LFSR called an MISR (multiple input signature register), for inputting them in parallel. In the VLSI and ULSI, the latter LFSR is overwhelmingly important. The following descriptions are therefore made in connection with the LFSR called MISR.
An example of an n-bit parallel input type LFSR (n=8) is shown in FIG. 2. As shown in FIG. 2, the input terminal D of bit 0 of the LFSR is supplied with an XOR signal of an output signal FB of the feedback circuit and an external data signal IN0 of the bit 0. The input terminals D of the F/F of bits 1 to 7 are supplied with an XOR signal of a signal output from the output Q of the F/F of the preceding bit and an external data signal IN of the very bit. The output signal FB is an XOR signal of a signal Q.sub.0 output from output terminal Q of the F/F of bit 0, a signal Q.sub.5 output from output terminal Q of the F/F of bit 5, a signal Q.sub.6 output from output terminal Q of the F/F of bit 6, and a signal Q.sub.7 output from output terminal Q of the F/F of bit 7. New data Q'.sub.i (i=0, 1, . . . , 7) are generated inside the LFSR and expressed by the following equations: EQU Q'.sub.0 =INO XOR FB (1) EQU Q'.sub.i+l =INn XOR Q.sub.i (i=0, 1, . . . 6) (2)
where XOR represents an XOR operation.
With the above circuit arrangement of the LFSR, since the signals output from the DUT are supplied in sequence to the LFSR storing a predetermined value, almost random data is generated in the F/F in response to the output signals and finally data of a certain test result is generated therein. The data generated in the LFSR is called a signature, while an operation of generating the signature by supplying the output signals of the DUT to the LFSR is called signature compression or signature analysis. In the signature analysis, the output signals of the DUT are signature-compressed using a series of data, and a test result (signature) finally left in the LFSR is compared with an expected value only once to judge whether the DUT is defect-free or not.
After the signature compression is executed using test data, the probability that the signature is correct, 1-2.sup.-n, which is obtained by subtracting the "aliasing" probability from 1. The "aliasing" is a phenomenon wherein the final signature (test result) becomes equal to that obtained by the correct output sequence of the DUT though some incorrect output are output during the test. Since, in general, the aliasing probability can be ignored when n is increased (n&gt;24), the reliability of signature analysis is extremely high in the VLSI and ULSI which process data of multiple bits (n.gtoreq.32).
The above-described is sometimes provided exclusively for the BIST, however, it can be often constructed from a normal operation type register in order to economize the test circuit.
Since the conventional LFSR described above was regarded as one circuit block, only the circuit operated in response to a single clock signal supplied from outside has been considered to be the LFSR. The BIST using the LFSR was first applied to circuits having a regular structure such as ROM, RAM and PLA. These circuits each correspond to a circuit block closed by a register or F/F, and their outputs are usually stored in an output register. In the BIST wherein an LFSR formed from the output register is used as a signature compression circuit, a delay in AC output of the DUT can be checked at the same time.
Not in the above circuit block having a regular structure but in a so-called random logic, if a DUT having a structure closed by a register or F/F whose system clocks are changed at the edges thereof can be achieved (an unimportant signal can be set to a fixed value during the BIST), the BIST can be effectively implemented. Such a BIST has been employed depending on the situation.
In the I/O (input/output) section of a commonly-used LSI, an output signal of the LSI is delayed by a predetermined period of time based on the edges of system clocks. For this reason, the conventional BIST using an LFSR operated at the edge of system clock is applied to the output terminal of the LSI, a logical value can be checked by the LFSR at the timing when data is sampled (at the edge of the system clock), but a delay in AC output of the DUT cannot be detected.
Basically, the application of the conventional BIST to the I/O terminal of the LSI cannot be achieved, including an important process of checking a delay in AC output.
There is very strong possibility that a method of improving the performance of VLSI or ULSI by mixing circuit blocks operated in synchronization with a plurality of clocks (including the same clocks having different edges) therein will become important. In the BIST using the conventional LFSR, since the LFSR requires a sufficient bit length in order to decrease the Aliasing probability to such a negligible extent, an extra F/F has to be added to each group of registers and F/F, with the result that the LFSR is increased in area.
To avoid such an overhead cost, the application of the BIST was likely to be given up.